TKT-1426 Digital design for FPGA
Exercise Timetable

Exercise rules

tkt1426_09_lib library

Weekly exercise sessions


Exercise work: calculator

Most of the exercises consist of making parts for a simple calculator capable of basic arithmetic and logic operations with limited operand and result size.

Exercise deadlines (and exercises)are moved by one week, because of the account activation delays... (correct deadlines are listed below)

Wiring diagram of the project. Picture of what pieces will be done on which exercises.

WeekEx#Design toolMain topicsDeadline
36 1HDL Designer HDL Designer, Modelsim and Quartus tutorial 16.09.2012
37 2HDL Designer Examining generated VHDL, debugging elevator controller 23.09.2012
38 3HDL Designer Keypad handler 30.09.2012
39 4 HDL Designer Bin to/from BCD conversion, timing analysis
40 4HDL Designer Bin to/from BCD conversion, timing analysis 28.10.2012
41 5HDL Designer LCD controller 1.11.2012
42 Exam week, assistant available on TC417 on exercise hours
43 6VHDL BCD register and ALU 11.11.2012
44 7VHDL Testbench for BCD register 11.11.2012
45 8Designer or VHDL Calculator input FSM 18.11.2012
46 9Pen and paper Manual synthesis 25.11.2012
47 10HDL Designer Putting things together ASSISTANT NOT AVAILABLE on 28.11, due influensa
48 10HDL Designer Putting things together 09.12.2012
49 BONUS 1VHDL FIFO 09.12.2012
BONUS 2Quartus II Setting up Quartus II project 09.12.2012