TKT-1426 Digital design for FPGA
Exercise 3



Task 1: Key encoder

Description:

Design a module that encodes pressed keys to the given format.

Requirements and specifications:

Tips:

Pen, paper and some optimization might be useful.
If your design's complexity measured in 2-input gates (and not counting inverters) seems to get way over 40, there is propably an easier way.

Return:

Pictures taken from the simulator showing correct behaviour.


Task 2: Key poller & debouncer FSM

Description:

This FSM polls keypad for detecting keypresses and takes care of contact bounce by waiting after every transition detected before polling again.

More about contact bounce at Wikipedia.

Requirements and specifications:

Tips:

Return:

Pictures taken from the simulator showing correct behaviour.


Task 3: Keypad handler

Description:

Now it is time to put pieces together, add some little logic and registers and test how our keypad handler works on FPGA.

Input from the keypad is asynchronous and thereby will eventually violate the setup and hold times of the input side logic. Input is synchronized with two flip-flops reducing the chance for metastable state propagating through the handler.

Due to the pull-up resistors floating lines (keypad_row_in in this case) are pulled to logical one and we have to poll the keypad with one column signal being zero and others one to detect if there is any conductive paths between column and row signals. Pressing more than one key down on the same row short circuits corresponding polling column signals so we have to drive only one column signal low and let the others float at high impedance state. This is achieved with tri-state buffers.

Keypad handler generates a one clock cycle pulse to inform the calculator's control logic that a key has been pressed. The encoded key and its type are kept at the output as long as the next key is being pressed down.

Requirements and specifications:

Return:

Pictures taken from the simulator showing correct behaviour.


Returning exercise: