[Back to Main Page]

TKT-2431 SoC design
Exercises 2012

[Back to previous]
This course emphasizes practical, hands-on work with a simple SoC implemented on an FPGA. Therefore, the exercises 1-12 are mandatory.

You need
  • access rights to computer class TC417/TC419. Return the application form to Timo Rintakoksi mailbox (Tietotalo 3rd floor between G and H wings).
  • Birdland account
Students can borrow an FPGA development kit, see detailed instructions in Finnish or application form in English.
Exercise rating system
Acceptance status
Exercise schedule

Current TOP 4 frame rates:

  1. : 347 fps @ 90 MHz (G21)
  2. : 101.13 fps (G10)
  3. : 89 fps (G03)
  4. : 87.42 fps (G16)
If your result is missing, please let us know immediately.

Email your exercise returns to tkt2431 (št) cs.tut.fi

  1. Week 36: Introduction to the topic and algorithms
  2. Week 37: Specifying the system (Rated exercise)
  3. Week 38: Software implementation of the system
  4. Week 39: Introduction to the Altera DE2 Development and Education board
  5. Week 40: Implementing the encoder on FPGA (Rated exercise)
  6. Week 41: Profiling the system performance on FPGA

  7. Week 42: Exam week - no exercises

  8. Week 43: Integrating the hardware accelerator to the architecture
  9. Week 44: Verifying that the accelerated system works
  10. Week 45: Designing the software to control the hardware accelerator
  11. Week 46: Profiling the accelerated system
  12. Week 47: Optimizing the accelerated system
  13. Week 48: Demonstration and final report (Rated exercise)
  14. Week 49: Demonstrations, assistance available (No new topic on this week)
  15. Week 50: Assistance available for boomerangs (No new topic on this week)

Last Modified: by Antti Alhonen