[Back to Opetus - Teaching] 

TIE-50206 Logic Synthesis

2016-2017 Periods 2-3, 5 cr.


Lectures


Periods 2+3: First lecture Mon 24.10.2016
  • Mon 12-14 TB207 (3 times, 24.10, 31.10, 7.11)
  • Tue 12-14 SC105B


Lecturer Arto Perttula (@tut.fi)

The course descriptions in the study guide.
Note! All useful material is on these web pages instead of POP!




This course teaches the basic principles of digital design with hardware description langauge,. VHDL in our case. After completing the course, students can implement digital system according to given requirements..


[Back to previous]

Exercises

  • Arto Perttula (arto.perttula@tut.fi)
  • Timo Viitanen (timo.2.viitanen@tut.fi)
  • Joonas Multanen (joonas.multanen@tut.fi)
This course emphasizes practical hands-on training. You can earn up to 6 points to the exam, hence the maximum points are 30+6=36 pt.

Periods 2+3; Starting from the first week in computer classTC221
  • Mon 16-18 (TV)
  • Wed 10-12 (JM)
  • Wed 14-16 (AP)

Course requirements

  • Final exam or 2 midterm exams (max. 30pt)
  • Passed exercises, 0-6 points
  • During the final examination, you can do only the full exam or the 2nd midterm exam, not both.

Reading material



Last modified: