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TI-50206 Logic Synthesis

Fall 2017 - Lectures


Preliminary schedule. Slides will appear on this page at some point.

(earlier material in study year 2016-2017)

# DATE TIME ROOM TOPIC
1 24.10.2017 Tue 10-12 TB219 Course Organization, Introduction
2 26.10.2017 Thu 14-16 TB219 VHDL Basics #1 - Entity And Architecture
3 31.10.2017 Tue 10-12 TB219 VHDL Basics #2 - Process, Signal, Types
4 2.11.2017 Thu 14-16 TB219 VHDL Basics #3 - Packages, Libraries, Operators, Attributes
5 7.11.2017 Tue 10-12 TB219 VHDL: Combinatorial And Sequential Logic, Generics, Statements
6 9.11.2017 Thu 14-16 TB219 RTL Synthesis
7 14.11.2017 Tue 10-12 TB219 Finite State Machine (FSM)
8 16.11.2017 Thu 14-16 TB219 Test Bench Basics
9 21.11.2017 Tue 10-12 TB219 HDL Simulators
1028.11.2017 Tue 10-12 TB219 Reuse
Coding guidelines
e15.12.2017 Tue 10-12TB219 Midterm exam on topics of lecures 1-9
Students may have one A4 sheet of personal notes
Christmas holidays
11 9.1.2018 Tue 10-12 TB219 Miscellaneous Topics, e.g., Tri-State 'Z', Variables and Latches
12 16.1.2018 Tue 10-12 TB219 Clocking and Synchronization #1 - Clock Signal, Metastability
13 23.1.2018 Tue 10-12 TB219 Clocking and Synchronization #2 - Synchronizers
1430.1.2018 Tue 10-12 TB219 FPGA Technology
15 6.2.2018 Tue 10-12 TB219 System Design Trends
1613.2.2018 Tue 10-12TB219Reserve
1720.2.2018 Tue 10-12TB219Reserve
E/e2 1.3.2018 Thu 13-16 TBA Exam (full / 2nd midterm)
E/e2 25.4.2018 Wed 17-20 TBA Exam

(*) If slides have been updated after the first publication.

Other material

Material on internet:
(Note that some recommentations and practices might differ sligthly from course slides.)
Downloading papers from IEEE Xplore works only from computers connected tut.fi domain.
  1. VHDL Language Reference, Altium
  2. VHDL Designer's Guide, Doulos
  3. SynthWorks' VHDL Papers
  4. VHDL-93 BNF, Uni. Hamburg
  5. IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis, IEEE, 2004
  6. 1076.3-1997 IEEE Standard VHDL Synthesis Packages, IEEE, 1997
Code examples
 
Lecture 6: FSM examples of Traffic_light.zip (316 KB)
Lecture 11: SDRAM controller core, quartus II 9.1. Handbook, Vol 5




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