Download
All available packets released under LGPL.- Trace monitor (VHDL & C++
- Transaction Generator2 (TG2) (SystemC) (New version 2013-01-23)
- Traffic models for TG2 (XML).
- Traffic Generator (VHDL + Python)
Trace Monitor
Trace Monitor is our new low-level HW/SW toolset to assist in Network-on-Chip evaluation with adaptive accuracy. 100Mbit/s Ethernet connection is used to transfer monitoring data from any real system in realtime. This data can be further analyzed afterwards.
| Documentation | ||
|---|---|---|
| A. Alhonen et al. "A Scalable, Non-interfering, Synthesizable Network-on-Chip Monitor - Extended version", Microprocessors and MicrosystemsConference, 2013 |
Paper as pdf | Updated Jan 23, 2013 |
| Download | ||
| Trace Monitor (includes all HW, SW, documentation and an example trace) | trace_monitor_release_package_10_2011.zip | Updated October 5, 2011 |
Transaction Generator 2
Transaction Generator 2 is a SystemC simulator and traffic generator for architecture exploration and benchmarking. It generates traffic according to an abstract application and platform models for network-on-chip (NoC) models. It's designed to support interfacing NoCs described in RTL or higher abstraction levels, such as OCP-IP TLM sockets.
Transaction generator 2 and the related programs and network-on-chip models are released under LGPL licence. In addition to TG, the package includes approximate DRAM model (ADM), ExecutionMonitor for viewing the results, set of test applications for NoC benchmarking, and set of reference NoC implementations.
Snapshots from the TG package will be also published in OCP-IP site because the tool has been adopted by OCP-IP Network-on-chip benchmarking workgroup.
| Included programs | ||
|---|---|---|
| Transaction Generator 2 | SystemC simuator | |
| Execution Monitor | Visualization tool for viewing simulation (Java) | |
| Included reference Network-on-Chip models | ||
| FH Mesh 2D | Synthesizeable RTL VHDL | |
| FH Mesh 2D | RTL SystemC | |
| FH Mesh 2D | SystemC OSCI TLM 2.0 sockets | |
| FH Mesh 2D | SystemC OCP-IP TLM2 Kit TL3 sockets | |
| FH Crossbar | Synthesizeable RTL VHDL | |
| FH Ring | Synthesizeable RTL VHDL | |
| ase_mesh1 | Synthesizeable RTL VHDL | |
| Documentation | ||
| Brief introduction | sctg2_brief.pdf | Updated June 2, 2010 |
| L. Lehtonen et al. "Analysis of Modeling Styles on Network-on-Chip Simulation", Norchip Conference, Tampere, Finland, Nov. 2010 |
Paper as pdf | Updated Jan 23, 2013 |
| E. Pekkarinen et al. "A Set of Traffic Models for
Network-on-Chip Benchmarking" on Network-on-Chip Simulation", Norchip Conference, Tampere, Finland, Nov. 2011, pp 78-81 |
Paper as pdf | Updated Jan 23, 2013 |
| Download | ||
| Transaction Generator 2 | sctg_2013_01_23.zip | Updated Jan 23, 2013 |
Traffic Generator
Traffic Generator (TG) is an RTL VHDL-based tool for network performance evaluation on FPGA. Multiple Traffic Generators are instantiated on an FPGA chip. TGs communicate through the NoC under benchmarking, emulating the final communication case defined by simple yet powerful models of the system's communication behavior. These communication models can be configured at the run-time without the need of tedious logic synthesis every time.
Traffic generator and the related programs are released under LGPL licence.
| Included programs | ||
|---|---|---|
| Traffic Generator | VHDL files for simulation and synthesis | |
| TG NoC monitor | Additional NoC monitors that give further information of network usage | |
| TG Commander | A computer front-end for TG FPGA runtime configuration | |
| Documentation | ||
| PDF files for TG and Monitor usage | Included in the release package. | |
| System requirements | ||
| FPGA development board with RS-232 UART (serial port) | ||
| A computer with RS-232 UART | ||
| FPGA chip with at least 100k port equivalents (30k LUTs), preferably more | ||
| Download | ||
| Traffic Generator | traffic_generator_20091201.zip | Added December 1, 2009 |
| Test package with Hermes, Nocem and Wishbone NoCs | TG_noc_testpkg.zip | Added Feb 22, 2013 (pkg created in March 2011) |
Transaction Generator
Transaction Generator is a SystemC simulator for architecture exploration and benchmarking which composes the application and platform models as well as the mapping information. It can simulate the workload model on any Network-on-Chip model provided it has an OCP TL2 interface.
Transaction generator and the related programs are released under LGPL licence.
| Included programs | ||
|---|---|---|
| Transaction Generator | SystemC simulator | |
| Dynamic Arex | Frontend for Transaction Generator | |
| Execution Monitor | Visualization tool for simulation | |
| Tg2execmon | Feeds simulation results to Execution Monitor | |
| Documentation | ||
| Proposal slides | tut_noc_benchmark_proposition_v03.pdf | |
| XML model documentation | TG_SystemC_modeling_20091208.pdf | Updated December 8, 2009 |
| Download | ||
| Transaction Generator | transgen_20091106.zip | Updated November 6, 2009 |
| Example applications | example_applications.zip | Updated December 3, 2009 |